Power semiconductor drive circuit, power semiconductor circuit, and power module circuit device

ABSTRACT

A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2014-208662, filed on Oct. 10, 2014, theentire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a power semiconductor drive circuit, apower semiconductor circuit using the power semiconductor drive circuit,and a power module circuit device including the power semiconductorcircuit and other circuit devices mounted on a single assembly.

BACKGROUND

Power semiconductor elements may include, for example, IGBT (InsulatedGate Bipolar Transistor), power MOSTFET (Metal Oxide Semiconductor FieldEffect Transistor), MOSGTO (MOS Gate Turn-off Thyristor) and the like.Further, an Intelligent Power Module (hereinafter referred to as an IPM)may include a power semiconductor circuit integrating these powersemiconductor elements and a power semiconductor drive circuit forcontrolling gates of the power semiconductor elements, and circuitdevices other than the power semiconductor circuit, which are packagedin a single package.

FIG. 11 schematically shows a power semiconductor drive circuit, a powersemiconductor circuit and a power module circuit device. As shown inFIG. 11, drains D of transistors M2 and M3 are connected in common andthis common connection point is connected to a node HO and a gate G of atransistor PT1. Gates G of transistors M2 and M3 are connected in commonand an upper input signal HIN is applied to these common gates G via anupper driver UD. A power supply voltage VBB is applied to a source S ofthe transistor M2 via an external terminal VB. The power supply voltageVBB is a power supply voltage VCC supplied to an external terminal VCand a boost voltage generated in a bootstrap circuit BS. A source of thetransistor M3 is connected to a node VS.

The transistor PT1 is referred to as an upper power transistor and apower supply voltage VPP is applied to a drain D of the transistor PT1via an external terminal P. The gate G of the transistor PT1 isconnected to the node HO. A source S of the transistor PT1 is connectedto the node VS. A diode for free-wheeling (shown without a referencesign) is connected between the drain D and the source S of thetransistor PT1.

A transistor PT2 is generally referred to as a lower power transistorand is fabricated on a separate semiconductor substrate from thetransistor PT1 referred to as the upper power transistor. A wire LW madeof material such as aluminum or copper is used as a connector forconnecting the transistor PT1 and the transistor PT2. The wire LW has afirst end connected to the node VS and a second end connected to anoutput terminal OUT and a drain D of the transistor PT2. The wire LW hasan inductance component lw.

The drain D of the transistor PT2 is connected to the output terminalOUT, a source S of the transistor PT2 is connected to a ground electricpotential GND via an external terminal N, and a lower input signal LINis applied to a gate G of the transistor PT2. A diode for free-wheeling(shown without a reference sign) is connected between the drain D andthe source S of the transistor PT2, like the transistor PT1. Thetransistor PT2 is turned on/off complementarily with the transistor PT1.That is, the transistor PT1 is OFF when the transistor PT2 is ON, andthe transistor PT1 is ON when the transistor PT2 is OFF.

A capacitor CB for bootstrap is connected between the external terminalVC and the external terminal OUT. The external terminal OUT is connectedto an external load. As the external load, an inductor L1 is shown. Theinductor L1 directly indicates an inductor, for example, employed for aswitching regulator, a motor winding, and a three-phase winding used foran inverter.

In the power semiconductor drive circuit and the like shown in FIG. 11,if a switching speed of the transistor PT1 is high, problems may occurwhere a transient voltage ΔV is generated by the inductance component lwof the wire LW and the transistors M2 and M3 deteriorate or aredestroyed. In addition, if a switching speed of the transistor PT2 ishigh, gate capacitances Crss and Ciss of the transistor PT1 are chargedand a gate voltage of the transistor PT1 exceeds a threshold voltage Vthof the transistor PT1. Accordingly, the transistor PT1 which should beoriginally placed in an OFF state is self-turned on and athrough-current flows between the transistor PT1 and the transistor PT2,which may result in a problem of deterioration of the transistors PT1and PT2. In addition, without leading to the deterioration, power may bewastefully consumed, which may result in difficulty in achieving powersaving.

As a first solution to solve the above problems, the driving ability ofa voltage-driven element may be lowered by changing a switching elementof a parallel circuit when a gate voltage at the time of turning-onreaches a mirror voltage.

A second solution may include detecting a change in gate voltage by acomparing circuit and changing gate resistance based on the detection.

As a third solution to realize the compatibility of EMI noisesuppression and switching loss suppression at low costs, a power devicecontrol circuit may employ a time constant circuit composed of aresistive element and a capacitor, as a timer circuit so as to equalizeperiods taken for a gate voltage to reach a mirror voltage.

However, the first solution still has a risk of a breakdown of a gatedriver due to a surge or a transient voltage generated according to anoperation of switching from an ON state to an OFF state.

The second solution requires a relatively complicated timer circuit fordetecting a timing at which an element at a high electric potential sideis switched from OFF to ON or from ON to OFF, and setting apredetermined voltage based on this detection.

Although the third solution suppresses the EMI noise, it cannot expectto suppress breakdown of a power semiconductor drive circuit andswitching loss of a power semiconductor.

SUMMARY

According to one embodiment of the present disclosure, there is provideda power semiconductor drive circuit including: a parallel circuit whichis connected to a gate of a power semiconductor element and isconstituted by at least two transistors for setting gate resistance ofthe power semiconductor element; a gate voltage monitoring circuitconnected to the gate of the power semiconductor element and theparallel circuit, wherein a predetermined monitoring voltage is set inthe gate voltage monitoring circuit in order to monitor a gate voltageof the power semiconductor element; a signal delay circuit to delay anoutput signal of the gate voltage monitoring circuit; and a gate controlcircuit to change the magnitude of combined resistance of the parallelcircuit based on an output signal output from the signal delay circuit.

The combined resistance of the parallel circuit may be changed when thepower semiconductor element is turned off.

The monitoring voltage may be equal to or less than a mirror voltage ofthe power semiconductor element.

The combined resistance of the parallel circuit when the powersemiconductor element is turned off may be larger than the combinedresistance of the parallel circuit when the power semiconductor elementis in an OFF state.

The combined resistance of the parallel circuit may be changed after adelay time set in the signal delay circuit elapses.

The ON state and OFF state of the gate voltage monitoring circuit may becontrolled by a kill signal and an output signal of the gate voltagemonitoring circuit may be a result of a logical AND operation for thekill signal and the gate voltage applied to the power semiconductorelement.

The gate voltage monitoring circuit may be constituted by one or moreselected from a group consisting of a Schmitt trigger, a hysteresiscomparator, a window comparator, a comparator and an inverter.

The signal delay circuit may be an integration circuit including aresistor and a capacitor.

A predetermined threshold voltage may be set in the gate control circuitand the gate control circuit may output a result of a logical ANDoperation for a driving signal applied to the gate of the powersemiconductor element and the output signal output from the signal delaycircuit.

Assuming that a period from time t4, at which a mirror period of thegate voltage of the power semiconductor element is ended, to time t6, atwhich an output current flowing in the power semiconductor element issubstantially zeroed, is τ1 and a period from time t5, at which the gatevoltage becomes equal to the monitoring voltage, to time t8, at whichthe gate voltage becomes equal to the threshold voltage, is τ2, thecondition of τ2>τ1 may be set.

The power semiconductor element may include an upper power transistorconnected to a power supply terminal and a lower power transistorconnected to a ground electric potential, the upper power transistorbeing complementary to the lower power transistor, and assuming that aperiod from time t5, at which a gate voltage of the upper powertransistor becomes equal to the monitoring voltage, to time t8 at whichthe gate voltage of the upper power transistor becomes equal to thethreshold voltage, is τ2 and time t 10 is a time at which the gatevoltage of the upper power transistor when the lower power transistor isON, becomes equal to the monitoring voltage, the relationship may be(t10−t5)>τ2.

Assuming that a period from time t16, at which the gate voltage of theupper power transistor becomes equal to the monitoring voltage, to timet20, at which the upper power transistor begins to be turned off, is τ3and a period from time t16, at which the gate voltage of the upper powertransistor becomes equal to the monitoring voltage, to time t18, atwhich the threshold voltage set in the gate control circuit becomesequal to the level of the output signal of the signal delay circuit, isτ4, the condition of τ3>τ4 may be set.

The gate control circuit may include a first transistor, a secondtransistor, an logical AND circuit, a first node, a second node, and athird node, wherein a gate of the first transistor and a first end ofthe logical AND circuit are connected to the first node, wherein a drainof the first transistor, a drain of the second transistor, and a secondend of the logical AND circuit are connected to the second node, whereinan output terminal of the logical AND circuit and a gate of the secondtransistor are connected to the third node, and wherein the drivingsignal is applied to the first node and an output signal of the signaldelay circuit is output to the second node.

According to another embodiment of the present disclosure, there isprovided a power semiconductor circuit including: the above-describedpower semiconductor drive circuit; and a power semiconductor elementhaving a gate driven by the power semiconductor drive circuit.

The power semiconductor element may be an MOS transistor or IGBT.

The power semiconductor element may be made of one selected from a groupconsisting of silicon (Si), silicon carbide (SiC), and gallium nitride(GaN).

The power semiconductor element may further include a diode, and whereinthe diode is made of one selected from a group consisting of silicon(Si), silicon carbide (SiC), and gallium nitride (GaN).

The lower power transistor may be made of one selected from a groupconsisting of silicon (Si), silicon carbide (SiC), and gallium nitride(GaN).

The upper power transistor and the lower power transistor may befabricated on separate semiconductor substrates, and wherein adrain-source conduction path of the upper power transistor and adrain-source conduction path of the lower power transistor are coupledin series between the power supply terminal and the ground electricpotential.

The power semiconductor circuit may be used for one selected from agroup consisting of inverters for converting DC into AC, one or moremotor drive circuits, and switching power supply devices.

According to another embodiment of the present disclosure, there isprovided a power module circuit device including: the above-describedpower semiconductor circuit; and at least one electronic elementconstituting at least a bootstrap circuit.

The power module circuit device may be packaged in a single dual-linepackage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a first embodiment of the presentdisclosure.

FIG. 2 is a circuit diagram showing a second embodiment of the presentdisclosure.

FIG. 3 is a time chart at the time when the circuits shown in FIGS. 1and 2 are in normal operation.

FIG. 4 is a time chart at the time when the circuits shown in FIGS. 1and 2 deviate from normal operation.

FIG. 5 is a circuit diagram showing a third embodiment of the presentdisclosure.

FIG. 6 is a time chart of the third embodiment.

FIG. 7 is a time chart at the time of checking the operation shown inFIG. 6.

FIG. 8 is a detailed circuit diagram of the gate control circuit 7 usedin FIG. 6.

FIG. 9 is a circuit diagram showing one example of a power semiconductormodule circuit device according to the present disclosure.

FIG. 10 is a figure showing a comparison in driving loss between thepresent disclosure and the conventional technique.

FIG. 11 is a circuit diagram showing a portion of a conventional powersemiconductor drive circuit.

DETAILED DESCRIPTION

The present disclosure provides some embodiments of a powersemiconductor drive circuit, a power semiconductor circuit, and a powermodule circuit device, which are capable of preventing gate driverbreakdown caused by an induced voltage, a transient voltage or a jumpingvoltage generated by an inductance component of a wire according to ahigh-speed switching in a high-voltage and a large-current, particularlyat the time of transition from an ON state to an OFF state, i.e., at thetime of turn-off, and suppressing self-turning-on of a power transistorand switching loss.

First Embodiment

FIG. 1 shows a power semiconductor drive circuit, a power semiconductorcircuit, and a power module circuit device according to the presentdisclosure. A power semiconductor circuit 10A includes a powersemiconductor drive circuit 10 and a power module circuit device 100includes the power semiconductor circuit 10A. In other words, the powersemiconductor circuit 10A is constituted by the power semiconductordrive circuit 10 and transistors PT1 and PT2. In addition, the powermodule circuit device 100 is constituted by the power semiconductorcircuit 10A and at least a bootstrap circuit BS. The power modulecircuit device 100 may be referred to as “IPM.” For the bootstrapcircuit BS, both of a diode DB and a capacitor CB may not beincorporated in the power module circuit device 100, but for example,only an electronic element of the diode DB may be incorporated thereinand the capacitor CB may be disposed outside the power module circuitdevice 100. The bootstrap circuit BS may be constituted using electronicelements such as a resistor, a transistor, a switching element, acurrent source and the like, in addition to the diode and the capacitor.

The power module circuit device, i.e., IPM, may be generally consideredas a single IC formed of a single package incorporating various types ofICs and discrete components such as a diode, a resistor, an inductor, apower transistor and the like, which are fabricated on a semiconductorsubstrate. In FIG. 1, the power semiconductor drive circuit 10 isconstituted by one or more ICs fabricated on a semiconductor substrate.Gates G of the transistors PT1 and PT2 are controlled by the powersemiconductor drive circuit 10. The transistors PT1 and PT2 are activeelements fabricated on a separate semiconductor substrate from the powersemiconductor drive circuit 10, as well as discrete components. Althoughit is shown in the embodiment of the present disclosure that thetransistor PT1 and the transistor PT2 are formed on differentsemiconductor substrates, both transistors may be formed on the samesemiconductor substrate. The diode and capacitor used for the bootstrapcircuit BS are passive elements fabricated on a separate substrate fromthe power semiconductor drive circuit 10 and the transistors PT1 andPT2, as well as discrete components.

The power module circuit device 100 shown in FIG. 1 has externalterminals, specifically, an external terminal VC as a first power supplyterminal, an external terminal P as a second power supply terminal, anexternal terminal OUT as an output terminal, and an external terminal Nas a ground terminal. The power module circuit device 100 further has anexternal terminal VB for supplying a boosted voltage in order to drivean upper driver UD. In addition to these external terminals, the powermodule circuit device 100 further has external terminals to which anupper input signal HIN and a lower input signal LIN supplied from an MCU(not shown) are input.

As described above, the power module circuit device 100 may beapparently considered as a single IC since it is formed of a singlepackage incorporating ICs and other discrete components. The powermodule circuit device 100 is incorporated in a so-called dual-linepackage (DIP) with two opposing sides of the package on which externalterminals are arranged. The power module circuit device 100 can be madecompact by being packaged in the DIP. In addition, when the power modulecircuit device 100 is packaged in the DIP, sides on which the externalterminals are not arranged can be effectively used as a wiring area.

The transistors PT1 and PT2 may employ, for example, power MOStransistors and IGBTs as power semiconductor elements. For example, asemiconductor substrate on which a power MOS transistor is fabricatedmay be formed of not only silicon (Si) but also, for example, siliconcarbide (SiC) or gallium nitride (GaN).

Although the transistor PT1 and the transistor PT2 are prepared as powersemiconductor elements, they have different roles in circuit operation.The transistor PT1 has the role to supply a load current to an inductorL1 serving as a load and the transistor PT2 takes responsibility fordrawing a load current to be supplied to the inductor L1 from an upperpower transistor, which is separate from the transistor PT1. Asdescribed previously, the transistors PT1 and PT2 are generally referredto as the upper power transistor and the lower power transistor,respectively. The term “upper” used herein means that the transistor PT1is connected to the power supply terminal side and the term “lower” usedherein means that the transistor PT2 is connected to the ground terminalside. Also, generally in the circuit diagram, when viewed from front, inmany cases, the upper power transistor is disposed in the upper side andthe lower power transistor is disposed in the lower side.

The transistors PT1 and PT2 shown in FIG. 1 are both formed of aconductivity type of NMOS transistor. A drain D of the transistor PT1 isconnected to the external terminal P as the second power supply terminaland a source S of the transistor PT1 is connected to a drain D of thetransistor PT2 with a common connection point therebetween connected tothe output terminal OUT. A source S of the transistor PT2 is connectedto a ground electric potential GND via the external terminal N.Alternatively, without being directly connected to the ground electricpotential GND, the source S of the transistor PT2 may be connected tothe ground electric potential GND via a current detection resistor. Agate G of the transistor PT2 is supplied with the lower input signal LINvia a lower driver LD. A diode for free-wheeling (shown without areference sign) is formed between the drain D and the source S of eachof the transistors PT1 and PT2. In general, the diode for free-wheelingmay be a so-called parasitic diode which is parasitically formed in eachof the transistors PT1 and PT2.

The transistors PT1 and PT2 operate in a complementary manner. That is,the polarity of a driving signal applied to the gate G of each of thetransistors PT1 and PT2 is set in such a manner that the transistor PT2is OFF when the transistor PT1 is on, and the transistor PT1 is OFF whenthe transistor PT2 is ON. In addition, so-called dead time for whichboth transistors are simultaneously off is set so that a through-currentmay not flow between the transistors PT1 and PT2 and both transistorsmay not deteriorate or be broken.

The source S of the transistor PT1 and the drain D of the transistor PT2are connected in common and the common connection point therebetween isconnected to the output terminal OUT. As described above, in theembodiment of the present disclosure, the source S of the transistor PT1and the drain D of the transistor PT2 are connected by a wire LW made ofmaterial such as aluminum or copper. The wire LW has an inductancecomponent lw. The output terminal OUT is coupled with, for example, aninverter for converting DC into AC, and for example, the inductor L1such as a switching regulator or a three-phase winding of a three-phasemotor. The inductor L1 may be broadly considered as an external load.

The power semiconductor drive circuit 10 is constituted by a single ICformed by integrating transistors M2, M3, and M4, a gate voltagemonitoring circuit 5, a signal delay circuit 6, a gate control circuit7, and so on.

The transistor M2 is a PMOS transistor and the transistor M3 and thetransistor M4 are NMOS transistors. The transistor M2 and the transistorM3 play the role of a gate driver to drive the transistor PT1. For thetransistors M3 and M4 both formed of the NMOS transistors, drain(D)-source (S) conduction paths of both transistors are connected inparallel with each other and are also connected in parallel to a gate(G)-source (S) conduction path of the transistor PT1. A parallel circuitconstituted by at least two transistors including the transistors M3 andM4 sets a gate resistance when the transistor PT1 is off. Of course, inorder to adjust the gate resistance, a resistor may be connected inseries to the source S side or drain side D of at least one of thetransistors M3 and M4. Combined resistance caused when the transistor M3is ON and the transistor M4 is OFF is approximately equal to the ONresistance of the transistor M3. Combined resistance caused when thetransistors M3 and M4 are simultaneously on corresponds to a parallelresistance of the ON resistances of the transistor M3 and the transistorM4. The combined resistance caused when the transistors M3 and M4 aresimultaneously on is smaller than that caused when only the transistorM3 is on. In addition, in order to change the gate resistance when thetransistor PT1 is OFF, a resistive element and a transistor may beconnected in parallel or in series and the resistances of them may bechanged in addition to the parallel circuit of the transistors M3 andM4.

The source S of the transistor M2 is connected to the external terminalVC as the first power supply terminal. The drain D of the transistor M2is connected in common to the drain D of the transistor M3 and a commonconnection point HO therebetween is connected to the gate G of thetransistor PT1. The gate G of the transistor M2 is connected in commonto the gate G of the transistor M3, a common connection point HBtherebetween is connected to an output of an inverter INV1, and an upperinput signal HIN is input to an input of the inverter INV1 via an upperdriver UD. The upper input signal HIN is a driving signal applied to thegate G of the transistor PT1.

The gate resistance when the transistor PT1 is OFF is greatly involvedin switching characteristic and power consumption of the transistors PT1and PT2, power consumption of the power semiconductor circuit 10A andthe power module circuit device 100, and the breakdown voltage of thegate driver constituted by the transistors M2 and M3. Smaller gateresistance is disadvantageous to the breakdown voltage of thetransistors M2 and M3, although it provides faster switchingcharacteristics and less power consumption of the transistor PT1. On theother hand, larger gate resistance is advantageous to the breakdownvoltage of the transistors M2 and M3, although it provides slowerswitching characteristics and more power consumption of the transistorPT1.

The gate voltage monitoring circuit 5 is connected to the commonconnection point HO, i.e., the gate G side of the transistor PT1. Thegate voltage monitoring circuit 5 is turned on/off based on apredetermined monitoring voltage Vk set in the gate voltage monitoringcircuit 5. Here, the monitoring voltage Vk is set to be equal to or lessthan a mirror voltage Vm generated in the mirror period of thetransistor PT1. Setting the monitoring voltage Vk is one of many veryimportant factors. This is because the magnitude of the monitoringvoltage Vk is used to determine the switching timing of the gateresistance of the transistor PT1. If the monitoring voltage Vk is set tobe more than the mirror voltage Vm, a change in current per time (di/dt)of the transistor PT1 is increased and there may be a problem caused inwhich a jumping voltage (an induced voltage or a transient voltage)caused by the inductance component lw of the wire LW exceeds thebreakdown voltage of the transistors M2 and M3. The magnitude of themirror voltage Vm and the length of the mirror period are varieddepending on the kind of power semiconductor elements, conductivitytype, size of transistor, and the like employed for the transistors PT1and PT2. In addition, some variations may occur for the sameconductivity type. Since the mirror voltage Vm may be varied dependingon the configuration and implementation status of peripheral circuitsand the operation conditions such as working temperature, there is aneed to take a certain degree of margin on implementation.

An output signal V5 of the gate voltage monitoring circuit 5 is input tothe signal delay circuit 6. The signal delay circuit 6 is provided toprevent a circuit at a subsequent stage from deviating from its inherentcircuit operation due to noise components included in the output signalV5. In addition, the signal delay circuit 6 has the function todetermine a delay time of signal transmission and ensures that when thetransistor PT1 is transitioned from ON to OFF, the gate resistance ofthe transistor PT1 is changed after a drain-source current id(hereinafter referred to as an output current id) flowing between thedrain and source of the transistor PT1 becomes zero.

An output signal V6 of the signal delay circuit 6 and an inverted signalHINB of the upper input signal HIN are input to the gate control circuit7. An output signal V7 of the gate control circuit 7 is input to thegate G of the transistor M4 and turns on/off the transistor M4. Forexample, when the output signal V7 has a high level H and a low level L,the transistor M4 is tuned on and off, respectively.

The gate control circuit 7 also has the action to complement the circuitoperation of the signal delay circuit 6, i.e., the function to furthersuppress and eliminate the noise components. In order to suppress andeliminate the noise components, a threshold voltage Vz is set in thegate control circuit 7. When the output signal V6 is less than thethreshold voltage Vz, the output signal V7 becomes the high level H toturn on the transistor M4, thereby lowering the gate resistance causedwhen the transistor PT1 is OFF.

Although it is illustrated in the first embodiment that the gate voltagemonitoring circuit 5, the signal delay circuit 6, the gate controlcircuit 7, and the transistor M4 are provided in the side of thetransistor PT1 serving as the upper power transistor, they may beprovided in the side of the transistor PT2 serving as the lower powertransistor.

The power semiconductor drive circuit, the power semiconductor circuit,and the power module circuit device according to the present disclosurecan be applied to inverters for converting DC into AC, drive circuits ofvarious types of motors, switching power supply devices, and the like.

Second Embodiment

FIG. 2 shows a second embodiment of the present disclosure. FIG. 2 showsthe internal circuits of the gate voltage monitoring circuit 5, thesignal delay circuit 6, and the gate control circuit 7 shown in FIG. 1(the first embodiment) in more detail. The same portions as FIG. 1 aredenoted by the same reference numerals and explanation of which will notbe repeated.

The gate voltage monitoring circuit 5 shown in FIG. 2 is constituted bya Schmitt trigger STS. The gate voltage monitoring circuit 5 may beconstituted by one of a hysteresis comparator, a window comparator, acomparator and an inverter, or a combination of at least one of them anda logical OR circuit, a logical AND circuit, an inverting circuit, orother logic circuits, instead of the Schmitt trigger. In the same manneras described above, the monitoring voltage Vk is set to be equal to orless than the mirror voltage Vm of the transistor PT1 in the gatevoltage monitoring circuit 5.

The signal delay circuit 6 is constituted by a resistor R63 and acapacitor C64. As described previously, the signal delay circuit 6 isprovided to delay the output signal V5 output from the gate voltagemonitoring circuit 5 in order to prevent a circuit at a subsequent stagefrom malfunctioning. In addition, since noise components such as aninduced voltage, a transient voltage and a jumping voltage occur in thegate G of the transistor PT1 due to the switching of the transistor PT1and the inductance component lw of the wire LW, the signal delay circuit6 is very useful for suppression and elimination of these noisecomponents and has the effect of significantly reducing risks ofmalfunction, deterioration, and destruction of the power module circuitdevice 100. In addition, since a signal delay time is determined by acombination of the resistance of the resistor R63 and the capacitance ofthe capacitor C64, it is ensured that when the transistor PT1 istransitioned from ON to OFF, the gate resistance of the transistor PT1when the transistor PT1 is OFF is decreased after an output current idof the transistor PT1 becomes zero.

The gate control circuit 7 is constituted by a logical AND circuit 73.The logical AND circuit 73 is a circuit which outputs a result of alogical AND operation for the output signal V6 of the signal delaycircuit 6 and the inverted signal HINB of the upper input signal HIN.The gate control circuit 7 can prevent the transistors M3 and M4 frombeing simultaneously transitioned when the upper input signal HIN istransitioned, thereby preventing the transistors M2 and M4 from beingsimultaneously ON. In addition, the Schmitt trigger may be provided in asubsequent stage of the logical AND circuit 73.

FIG. 3 is a time chart according to the first and second embodimentsshown in FIGS. 1 and 2. FIG. 3 is applied in common to FIGS. 1 and 2.

A graph of (a) of FIG. 3 shows the upper input signal HIN. The upperinput signal HIN is applied to the transistors M2 and M3 and the gatecontrol circuit 7 via the upper driver UD and the inverter INV1.

A graph of (b) of FIG. 3 shows the lower input signal LIN. The lowerinput signal LIN is applied to the gate G of the transistor PT2 via thelower driver LD. The lower input signal LIN is set to have, for example,a high level H when the upper input signal HIN has a low level L. Therealso exists a period during which the upper input signal HIN is set tohave the low level L when the lower input signal LIN has the low levelL. That is, a period for which both of the input signals have the lowlevel L is provided. This period is a so-called dead time for which thetransistors PT1 and PT2 are simultaneously OFF.

A graph of (c) of FIG. 3 shows a gate voltage Vho generated in the gateG of the transistor PT1 serving as the upper power transistor. The gatevoltage Vho behaves responsive to the upper input signal HIN. At timet1, the upper input signal HIN is turned off. That is, although theupper input signal HIN is transitioned from the high level H to the lowlevel L at time t1, the level of the gate voltage Vho begins togradually fall from time t2 delayed a little from time t1. The level ofthe gate voltage Vho becomes substantially constant in a period fromtime t3 to time t4, which is referred to as a mirror period. A voltagelevel at which the magnitude of the gate voltage Vho is constant isgenerally referred to as a mirror voltage. When time t5 elapses afterpassing through time t4 of the mirror period, the gate voltage Vho issubstantially 0V at time t7 through time t6 corresponding to a thresholdvoltage Vth. Time t5 indicates a time at which the gate voltage Vhoreaches the monitoring voltage Vk set in the gate voltage monitoringcircuit 5. Time t6 indicates a time at which the gate voltage Vhoreaches a gate threshold voltage Vth of the transistor PT1. The durationfrom time t4 to time t6 is indicated by a period τ1. That is, the periodτ1 corresponds to a relatively short period taken until the gate voltageVho of the transistor PT1 reaches the gate threshold voltage Vth of thetransistor PT1 after reaching the monitoring voltage Vk. In the periodτ1, the transistor PT1 is in an ON state immediately before entering anOFF state.

After passing through time t7, the gate voltage Vho shows a state wherea spike-like noise Vn1 occurs at a period from time t10 to time tn.Rather than the gate voltage Vho in the stationary state, the spike-likenoise Vn1 is schematically shown to be superimposed on the gate voltageVho. The noise component schematically shows a state where it occurs ata timing at which the transistor PT2 is ON, that is, in a period fromtime t10 to time t11 delayed a little from time t9 at which the lowerinput signal LIN shown in the graph of (b) of FIG. 3 becomes the highlevel H. When the lower input signal LIN is changed from the low level Lto the high level H at time t9, if there is no signal delay, thetransistor PT2 will enter an ON state at the same time as time t9.However, the transistor PT2 is actually ON after time t9 and it is shownthat a period during which a noise exceeding the monitoring voltage Vkoccurs in the gate of the transistor PT1 by the turning-on of thetransistor PT2 is the period from t10 to time tn. Assuming that thesignal delay time is zero, time t10 is the same as time t9. Afterpassing through time t11, the gate voltage Vho of the transistor PT1gradually rises at a timing at which the upper input signal HIN istransitioned from the low level L to the high level H, that is, fromtime t14 delayed a little from time t13 at which the upper input signalHIN is turned on. After passing through time t15 at which the outputcurrent id of the transistor PT1 is again flown and time t16 at whichthe gate voltage Vho reaches the monitoring voltage Vk set in the gatevoltage monitoring circuit 5, the gate voltage Vho rises until time t17at which the mirror period begins. Assuming that a timing at which theupper input signal HIN is again transitioned from the high level H tothe low level L is time t19, the gate voltage Vho begins to fall againfrom time t20 delayed a little from time t19. The duration from time t16to time t20 is indicated by a period τ3.

A graph of (d) of FIG. 3 shows the output current id flowing in thetransistor PT1. The output current id is responsive to the gate voltageVho shown in the graph of (c) of FIG. 3. Although maintained at maximumup to time t4 of the deep ON period (i.e., the mirror period) of thetransistor PT1, the output current id is decreased in response todecreasing of the gate voltage Vho. When the gate voltage Vho fallsbelow the gate threshold voltage Vth of the transistor PT1, thetransistor PT1 approaches to an OFF state and ultimately, the outputcurrent id becomes about zero near time t7 at which the gate voltage Vhoof the transistor PT1 becomes 0V.

A graph of (e) of FIG. 3 shows the output signal V5 of the gate voltagemonitoring circuit 5. The output signal V5 has a high level H when thegate voltage Vho is higher than the monitoring voltage Vk set in thegate voltage monitoring circuit 5, and has a low level L when the gatevoltage Vho is lower than the monitoring voltage Vk. Therefore, theoutput signal V5 has a high level H in periods from time t1 to time t5,time t10 to time t11, and time t16 to time t22, and has a low level L inperiods from time t5 to time t10, time t11 to time t16 and after timet22. A period T1 shown in the graph of (e) of FIG. 3 indicates a periodfrom time t5 at which the gate voltage monitoring circuit 5 begins tooperate to time t10 at which a noise component Vn2 occurs. This periodis also a period during which an integration circuit forming the signaldelay circuit 6 to be described later is discharged.

A graph of (f) of FIG. 3 shows the output signal V6 of the signal delaycircuit 6. The output signal V6 gradually falls from a falling timing ofthe output signal V5 shown in the graph of (e) of FIG. 3, i.e., time t5,toward time t14. The level of the output signal V6 is lowered since theintegration circuit forming the signal delay circuit 6 continues to begradually discharged until the upper input signal HIN is transitioned tothe high level H, based on a time constant of the integration circuit.Although the output signal V6 rises slightly in a period from time t10to time t11 by a noise Vn3 on the way, it again falls since the pulsewidth of the noise Vn3 is narrow.

The output signal V6 gradually falls even after it exceeds the thresholdvoltage Vz set in the gate control circuit 7. The duration from time t5to time t8 at which the output signal V6 reaches the threshold voltageVz is indicated by a period τ2. When the output signal V6 falls belowthe threshold voltage Vz, the gate control circuit 7 outputs an outputsignal V7 to turn on the transistor M4.

A circuit constant of the signal delay circuit 6 is set such that theperiod τ2 is larger than the period τ1 mentioned in the graph of (c) ofFIG. 3, i.e., τ2>τ1. According to such condition setting, a timing atwhich the transistor M4 is transitioned from OFF to ON can be set afterthe output current id of the transistor PT1 is zeroed. In other words,the gate resistance when the transistor PT1 is OFF can be transitionedfrom a high level H (the ON resistance of the transistor M3) to a lowlevel L (the parallel ON resistance of the transistors M3 and M4) afterthe output current id of the transistor PT1 is zeroed. This allows thedi/dt value of the transistor PT1 to be reduced, thereby suppressing atransient voltage Δv caused by the inductance component lw of the wireLW and further suppressing breakdown voltage deterioration of thetransistors M2 and M3.

Although the magnitude relationship between the period τ2 shown in thegraph of (f) of FIG. 3 and the period τ1 shown in the graph of (c) ofFIG. 3 is as described earlier, the relationship between the period τ2and the period T1 is set to meet the condition of τ2<T1. The period T1is the period from time t5 to time t10. That is, T1=t10−t5. Time t10 isa time at which the noise component Vn is assumed to occur. However, thenoise components Vn1 to Vn3 may occur in the time t9 to t12 periodduring which the lower input signal LIN shown in the graph of (b) ofFIG. 3 is transitioned from the low level L to the high level H.Therefore, also when the noise components Vn1 to Vn3 occur at time t9,the circuit constant of the signal delay circuit 6 has to be set toallow the signal delay circuit 6 to sufficiently suppress and attenuatethe noise components Vn1 to Vn3 included in the output signal V5 inputfrom the gate voltage monitoring circuit 5, so that the noise componentVn3 included in the output signal V6 output from the signal delaycircuit 6 falls below the threshold voltage Vz. When this settingcondition is satisfied, when the transistor PT2 is transitioned from OFFto ON (i.e., so-called turned ON) by the lower input signal LIN, it ispossible to suppress excessive rising of the gate voltage of thetransistor PT1 by dV/dt (change in voltage per time) of the transistorPT2 and further to eliminate the problem of the self-turn ON of thetransistor PT1. The output signal V6 rises gradually from a risingtiming of the output signal V5 shown in the graph of (e) of FIG. 3,i.e., time t16, toward time t22. A period from time t16 to time t18 atwhich the output signal V6 reaches the threshold voltage Vz is indicatedby τ4. A time at which the output signal V6 has the same level as thethreshold voltage Vz may not be time t18 but may be put between time t16and time t17 which are earlier than time t18.

The circuit constant of the signal delay circuit 6 is set such that theperiod τ4 is smaller than the period τ3 shown in the graph of (e) ofFIG. 3, i.e., τ3>τ4. In other words, assuming that a period from timet16 at which the gate voltage Vho of the transistor PT1 is equal to themonitoring voltage Vk to time t20 at which the transistor PT1 begins tobe turned off is τ3 and a period from time t16 at which the gate voltageVho of the transistor PT1 is equal to the monitoring voltage Vk to timet18 at which the threshold voltage Vz set in the gate control circuit 7is equal to the level of the output signal V6 of the signal delaycircuit 6 is τ4, the circuit constant of the signal delay circuit 6 isset to meet the relationship of τ3>τ4. According to such conditionsetting, when the transistor PT1 is transitioned to OFF, the transistorM4 is OFF, i.e., the gate resistance of the transistor PT1 is maintainedat a high level H. In the same manner as described above, this allowsthe di/dt value of the transistor PT1 to be reduced, thereby suppressinga transient voltage Δv caused by the inductance component lw of the wireLW and the like and further suppressing breakdown voltage deteriorationof the transistors M2 and M3.

A graph of (g) of FIG. 3 shows an ON/OFF state of the transistor M3along with the gate voltage of the transistor M3. The gate voltage ofthe transistor M3 is substantially equal to an inversion (in polarity)of the upper input signal HIN. The gate voltage of the transistor M3 istransitioned from a low level L to a high level H at time t2 delayed alittle from time t1 and is transitioned from the high level H to the lowlevel L at time t14 delayed a little from time t13. The transistor M3 isON in a period from time t2 to time t14.

A graph of (h) of FIG. 3 shows the output signal V7 of the gate controlcircuit 7. The output signal V7 is applied to the gate G of thetransistor M4. The output signal V7 is an operation result of a logicalAND operation for a voltage Vhb applied to the gate G of the transistorM3 and the output signal V6 output from the signal delay circuit 6. Theoutput signal V7 has a low level L in a period from time t1 to time t8and a high level H in a period from time t8 to time t14 and again hasthe low level L in a period from time t14 to time t25. The transistor M4is ON when the output signal V7 has the high level H, while being OFFwhen the output signal V7 has the low level L. At time t14 delayed alittle from time t13 at which the upper input signal HIN is turned on,since a signal of the node HB is input to a first end of the logical ANDcircuit 73 forming the gate control circuit 7, the logical AND circuit73 outputs the output signal V7 having the low level L, irrespective ofthe output signal V6 of the signal delay circuit 6. That is, since itcan be ensured that the transistor M4 and the transistor M3 are turnedoff substantially at the same time, it is possible to avoid simultaneousON of the transistor M4 and the transistor M2.

A graph of (i) of FIG. 3 shows the gate resistance of the transistorPT1. Here, the gate resistance is a resistance interposed between thegate G and source S of the transistor PT1. When the transistor M3 is ONand the transistor M4 is OFF, the gate resistance is relatively high (H)since the ON resistance of the transistor M3 becomes the gateresistance. On the other hand, when both of the transistor M3 and thetransistor M4 are ON, the gate resistance of the transistor PT1 isrelatively low (L) since the parallel resistance of the transistors M3and M4 becomes the gate resistance. The gate resistance of thetransistor PT1 is maintained at a low level L when the transistor PT2 isON. In a period x during which the transistors M3 and M4 are both OFF,only the transistor M2 is ON and accordingly the gate resistance whenthe transistor PT1 is OFF becomes high impedance.

FIG. 4 is a time chart in a case where the circuit constant of thesignal delay circuit 6 in the second embodiment (FIG. 2) of the presentdisclosure is not properly set.

Graphs (a) to (e) and (g) of FIG. 4 are substantially the same as thegraphs of (a) to (e) and (g) of FIG. 3, respectively, and therefore,explanation of which will not be repeated.

A graph of (f) of FIG. 4 shows the output signal V6 output from thesignal delay circuit 6. It is schematically shown in this figure thatthe output signal V6 includes a noise component Vn3 which is still alarger level than the threshold voltage Vz of the gate control circuit 7due to improper setting of the circuit constant of the signal delaycircuit 6. A voltage value of the output signal V6 of the signal delaycircuit 6 gradually rises a period from time t16 to time t22 duringwhich the output signal V5 of the gate voltage monitoring circuit 5 hasa high level H. If the boosting of the output signal V6 of the signaldelay circuit 6 is not yet completed at time t22, a delay time from timet22 to time t25 a at which the output signal V6 reaches the thresholdvoltage Vz is shortened and, therefore, the di/dt (change in current pertime) value of the transistor PT1 is likely to increase, as shown in thegraph of (c) of FIG. 4. It is advantageous to avoid the increase of thedi/dt value from the view of the breakdown voltage of the transistors M2and M3.

A graph of (h) of FIG. 4 shows the output signal V7 output from the gatecontrol circuit 7. It is shown in this figure that the output signal V7has a low level L in a period from time t10 a to time t11 a since thenoise component Vn3 shown in the graph of (f) of FIG. 4 is larger thanthe threshold voltage Vz, although the output signal V7 should beoriginally at a high level H even in the period from time t10 a to timet11 a.

A graph of (i) of FIG. 4 schematically shows the magnitude of the gateresistance of the transistor PT1. When the gate voltage monitoringcircuit 5, the signal delay circuit 6, and the gate control circuit 7are operating in the normal mode, the gate resistance has a low level Leven in the period from time t10 a to time t11 a. However, since thesetting of the circuit constant of the signal delay circuit 6 isimproper, the transistor M4 is placed in an OFF state in the period fromtime t10 a to time t11 a. This shows a state where the switching of thegate resistance of the transistor PT1 is not performed.

The above-described circuit configuration including the gate voltagemonitoring circuit 5, the signal delay circuit 6, the gate controlcircuit 7, and the transistor M4 according to the present disclosure issuitable to switch the gate resistance at the time of turning-off of thetransistor PT1 and ensure reduction of power loss and the breakdownvoltage of the gate driver, i.e., the transistors M2 and M3. However, asdescribed above, it should be noted that the original effect is reduced,particularly when the setting of the circuit constant of the signaldelay circuit 6 is improper.

Third Embodiment

FIG. 5 shows a third embodiment of the present disclosure. FIG. 5 showsthe gate voltage monitoring circuit 5 and the gate control circuit 7shown in FIG. 2 (the second embodiment) in more detail. The sameportions as FIGS. 1 and 2 are denoted by the same reference numerals andexplanation of which will not be repeated.

In the third embodiment according to the present disclosure, themonitoring voltage Vk is set in the gate voltage monitoring circuit 5,and the monitoring voltage Vk is set to be equal to or less than themirror voltage Vm of the transistor PT1. The gate voltage monitoringcircuit 5 is connected to the gate G of the transistor PT1 and anexternal terminal KILL, respectively and outputs a result of a logicalAND operation for the gate voltage Vho from the gate G of the transistorPT1 and a kill signal Ki applied to the external terminal KILL, as theoutput signal V5. The output signal V5 is input to the signal delaycircuit 6.

The gate voltage monitoring circuit 5 includes inverters INV51 and INV52and a logical NAND circuit NA53. An input of the inverter INV51 isconnected to the gate G of the transistor PT1, i.e., the node HO, and anoutput of the inverter INV51 is connected to a first end of the logicalNAND circuit NA53. The inverter INV51 is, for example, a CMOS inverter.The monitoring voltage Vk based on the switching characteristics of theinverter INV51 is set. The gate voltage Vho of the transistor PT1 isapplied to the first end of the logical NAND circuit NA53 via theinverter INV51. An input of the inverter INV52 is connected to theexternal terminal KILL. The kill signal Ki is applied to the externalterminal KILL. The kill signal Ki is set to a high level H or a lowlevel L. In this embodiment of the present disclosure, when the killsignal Ki has the low level L, the gate voltage monitoring circuit 5operates in the normal mode and the signal delay circuit 6 and the gatecontrol circuit 7 coupled to the subsequent stage of the gate voltagemonitoring circuit 5 also operate in the normal mode. When the killsignal Ki is set to the high level H, the circuit operation of the gatevoltage monitoring circuit 5 is interrupted and stopped. At this time,the signal delay circuit 6 and the gate control circuit 7 at thesubsequent stage are also interrupted and stopped.

The effect of the circuit operation of the gate voltage monitoringcircuit 5, the signal delay circuit 6, and the gate control circuit 7can be determined from a comparison between an output signal waveformand an output current waveform of the external terminal OUT provided asan output terminal when the kill signal Ki is set to the low level L andthe high level H.

The signal delay circuit 6 shown in FIG. 5 is constituted by the sameresistor R63 and capacitor C64 as the second embodiment (FIG. 2). Theresistor R63 and the capacitor C64 form an integration circuit, i.e., alow pass filter. This low pass filter may be composed of not only onestage but also a plurality of stages. The signal delay circuit 6 showsthe effect of suppressing and eliminating noise components Vn1 and Vn2included in the output signal V5.

The gate control circuit 7 is composed of an NMOS transistor M71, a PMOStransistor M72, a logical AND circuit 73, and an inverter INV74, unlikethe second embodiment (FIG. 2).

In the gate control circuit 7, the transistors M71 and M72 are connectedin series via a node N7. A gate G of the transistor M72 is connected tothe node HB and a first end of the logical AND circuit 73. A drain D ofthe transistor M72 is connected to a second end of the logical ANDcircuit 73, a drain D of the transistor M71, and the node N7. An inputof the inverter INV74 is connected to the node N7 and an output of theinverter INV74 is connected to the gate of the transistor M4 provided tochange the gate resistance of the transistor PT1. The inverter INV74 is,for example, a CMOS inverter. The threshold voltage Vz based on theswitching characteristics of the CMOS inverter is set. An output of thelogical AND circuit 73 is connected to the gate G of the transistor M71.The node N7 is connected to an output of the signal delay circuit 6,i.e., the common connection point between the resistor R63 and thecapacitor C64. The transistor M72 and the transistor M71 may be regardedas a CMOS inverter connected in series between the external terminal VBas a boot terminal and the external terminal OUT as an output terminal,and the node N7 may be regarded as an output terminal of the CMOSinverter. Therefore, an output signal of the signal delay circuit 6outputting the output signal V6 is a signal obtained by adding theoutput of the CMOS inverter and the output of the signal delay circuit6. In other words, the output signal V6 is controlled by the CMOSinverter.

FIG. 6 is a time chart of the third embodiment. FIG. 6 is similar asFIG. 3 except the following points. First, a voltage waveform of a graphof (f) of FIG. 6 is different from that of the graph of (f) of FIG. 3.Second, a graph of (g) of FIG. 6 shows an ON/OFF state of the transistorM71. Third, a graph of (h) of FIG. 6 shows an ON/OFF state of thetransistor M72. FIG. 6 shows signal waveforms obtained when the externalterminal KILL as the killer terminal shown in FIG. 5 is set to a lowlevel L and the gate voltage monitoring circuit 5, the signal delaycircuit 6 and the gate control circuit 7 are operated in the normalmode.

FIG. 6 is mostly the same as FIG. 3 described previously and therefore,explanation about the same portions will not be repeated. The graphs of(f), (g), and (h) of FIG. 6 will be described below.

The graph of (f) of FIG. 6 shows an output signal V6 output from thesignal delay circuit 6. The output signal V6 is sharply turned to a lowlevel L at time t8, and the low level L lasts to time t14. This propertyis very different from that in the period from time t8 to time t14 shownin the graph of (f) of FIG. 3. This is because the property in theperiod from time t8 to time t14 is determined by the characteristics ofthe CMOS inverter composed of the transistors M71 and M72 shown in FIG.5. As described above, at time t8, the output signal V6 of the signaldelay circuit 6 reaches the threshold voltage Vz of the gate controlcircuit 7, a high level H of the output signal of the logical ANDcircuit 73 is applied to the gate G of the transistor M71, and thetransistor M71 is accordingly turned on. At this time, the capacitor C64of the signal delay circuit 6 becomes short-circuited and the outputsignal V6 of the signal delay circuit 6 is sharply turned to a low levelL. That is, the CMOS inverter is used at time t8 to separate theswitching of the gate resistance at the time of turning-off of thetransistor PT1 from the characteristics of the signal delay circuit 6.

At time t14 delayed a little from time t13 at which the upper inputsignal HIN is turned on, since the transistor M72 of the CMOS invertergoes to an ON state and the transistor M71 goes to an OFF state, anelectric potential difference across the two ends of the transistor M71is directly applied across the two ends of the capacitor C64. Therefore,the capacitor C64 is rapidly charged and the output signal V6 of thesignal delay circuit 6 is sharply turned to a high level H, therebyeliminating a need of the above-mentioned condition of τ3>τ4.

A graph of (g) of FIG. 6 shows an ON/OFF state of the transistor M71.The ON period of the transistor M71 corresponds to a period from time t8to time t14. The period of low level L of the output signal V6 issubstantially equal to the ON period of the transistor M71.

A graph of (h) of FIG. 6 shows an ON/OFF state of the transistor M72.The ON/OFF of the transistor M72 is responsive to the high level H andlow level L of the upper input signal HIN. That is, the transistor M72is ON when the upper input signal HIN has the high level H, while beingOFF when the upper input signal HIN has the low level L.

FIG. 7 shows a time chart when the external terminal KILL in the thirdembodiment shown in FIG. 5 is set to a high level H, the gate voltagemonitoring circuit 5, the signal delay circuit 6, and the gate controlcircuit 7 are interrupted and stopped, and the transistor M4 is OFF inorder to check the extent of effects by a difference in magnitude of thegate resistance of the transistor PT1.

A graph of (a) of FIG. 7 shows the upper input signal HIN. It is hereshown that the upper input signal HIN is transitioned from a high levelH to a low level L at time t1.

A graph of (b) of FIG. 7 shows the kill signal Ki applied to theexternal terminal KILL. The kill signal Ki is set to be transitionedfrom a low level L to a high level H at time t0 earlier than time t1. Inthe embodiment of the present disclosure, the check function to checkthe magnitude of the gate resistance of the transistor PT1 according tothe present disclosure is performed when the kill signal Ki has the highlevel H, while the check function is being interrupted when the killsignal Ki has the low level L. Therefore, when the check function isperformed, the switching of the kill signal Ki is prioritized to theswitching of other signals or voltages. If the switching of the killsignal Ki from the low level L to the high level H is delayed from timet1, sufficient effects of the present disclosure cannot be expected.

When the kill signal Ki is switched from the low level L to the highlevel H at time to, the gate voltage monitoring circuit 5, the signaldelay circuit 6, and the gate control circuit 7 are interrupted andstopped by being separated from the normal mode after time t1.

A graph of (c) of FIG. 7 shows an ON/OFF state of the transistor M2. Thetransistor M2 operates in response to the upper input signal HIN shownin the graph of (a) of FIG. 7. When the upper input signal HIN has ahigh level H and a low level L, the transistor M2 is ON and OFF,respectively.

A graph of (d) of FIG. 7 shows an ON/OFF state of the transistor M3. Thetransistor M3 operates in response to the upper input signal HIN shownin the graph of (a) of FIG. 7. When the upper input signal HIN has thehigh level H and the low level L, the transistor M3 is OFF and ON,respectively. The ON/OFF state of the transistor M3 is complementary tothat of the transistor M2 shown in the graph of (c) of FIG. 7 from adifference in circuit configuration and conductivity type of thetransistor. Therefore, the transistor M3 is ON when the transistor M2 isOFF, and the transistor M3 is OFF when the transistor M2 is ON.

A graph of (e) of FIG. 7 shows the gate voltage Vho of the transistorPT1, i.e., the voltage of the node HO. The gate voltage Vho isresponsive to the turning-ON/OFF of the transistor M2 without beingaffected by the kill signal Ki shown in the graph of (b) of FIG. 7. Asshown in FIGS. 3 and 6 described previously, the gate voltage Vhogradually falls from time t2 toward time t3, maintains at approximatelya constant mirror voltage Vm in the mirror period from time t3 to timet4, and begins to further fall toward time t7 after passing through themirror period.

A graph of (f) of FIG. 7 shows the output signal V5 of the gate voltagemonitoring circuit 5. After time to, the operation of the gate voltagemonitoring circuit 5 remains interrupted and stopped by the kill signalKi, and therefore, the output signal V5 has a low level L. In addition,before time t0, the gate voltage monitoring circuit 5 is in the normalmode since the kill signal Ki has the low level L, but the output signalV5 has the low level L as well since this signal is in the dead timeperiod during which the transistors PT1 and PT2 are both OFF. A graph of(g) of FIG. 7 shows the output signal V6 of the signal delay circuit 6.Since no signal from the gate voltage monitoring circuit 5 at theprevious stage exist, the output signal V6 has a low level L like theoutput signal V5 in the signal delay circuit 6.

A graph of (h) of FIG. 7 shows the output signal V7 of the gate controlcircuit 7. The output signal V7 is applied to the gate G of thetransistor M4. The output signal V7 is generated based on the outputsignal V6 output from the signal delay circuit 6. Therefore, the outputsignal V7 has a low level L, like the output signal V6. At this time,the transistor M4 is placed in the OFF state.

A graph of (i) of FIG. 7 shows an ON/OFF state of the transistor M71constituting the gate control circuit 7. The transistor M71 is turnedon/off by the output signal of the logical AND circuit 73. Since thetransistor M71 is an NMOS transistor, the ON/OFF of the transistor M71is responsive to the gate voltage applied to the gate G thereof. Thatis, the transistor M71 is ON when the gate voltage of the transistor M71has a high level H, while being OFF when the gate voltage has a lowlevel L.

A graph of (j) of FIG. 7 shows an ON/OFF state of the transistor M72. Aninversion signal HINB of the upper input signal HIN is applied to thegate G of the transistor M72. Therefore, the ON/OFF of the transistorM72 is responsive to the upper input signal HIN shown in the graph of(a) of FIG. 7. That is, when the upper input signal HIN has the highlevel H and the low level L, the transistor M72 is ON and OFF,respectively.

A graph of (k) of FIG. 7 shows whether the gate resistance of thetransistor PT1 has a high level H or a low level L. When the transistorM3 is ON and the transistor M4 is OFF, the gate resistance of thetransistor PT1 has a high level H which is approximately equal to the ONresistance of the transistor M3. When the transistors M3 and M4 are bothON, the gate resistance of the transistor PT1 has a low level L.However, FIG. 7 shows the operations of a state where the gate voltagemonitoring circuit 5, the signal delay circuit 6 and the gate controlcircuit 7 are interrupted and stopped by the kill signal Ki, in whichthere exists no period during which the gate resistance of thetransistor PT1 is fixed at the low level L. Since a period x indicatedwith oblique lines is the dead time of the transistors PT1 and PT2 aswell as a period during which the kill signal Ki is applied, the gateresistance at the time of turning-off of the transistor PT1 becomes highimpedance.

FIG. 8 shows a modification of the gate control circuit 7 used for thethird embodiment (FIG. 5). The gate control circuit 7 shown in FIG. 8differs greatly from that shown in FIG. 5 in that a Schmitt trigger SHis connected between the node N7 and an input terminal of the inverter74.

In general, a Schmitt trigger has two threshold values for an inputsignal and is widely used to avoid a malfunction which may be caused bya noise component included in the input signal. The Schmitt trigger SHshown in FIG. 8 includes transistors M701, M702, M703, M704, M705, andM706. A conductivity type of the transistors M701 and M705 is PMOS and aconductivity type of the transistors M702, M703, M704, and M706 is NMOS.

A source S of the transistor M701 is connected to a power supplyterminal VB. Drains D of the transistors M701 and M702 are connected incommon and the common connection point thereof is indicated by the nodeN71. Gates G of the transistors M701 and M702 are connected in common tothe node N7. The output signal V6 output from the signal delay circuit 6is applied to the node N7. A source S of the transistor M702 isconnected to a drain D of the transistor M703. A common connection pointbetween the drain D of the transistor M703 and the source S of thetransistor M702 is indicated by a node N72. A source S of the transistorM703 is connected to a ground electric potential GND and a gate Gthereof is connected in common to the gate G of the transistor M702.

Gates G of the transistors M705 and M706 are connected in common to thenode N71 to which the drains D of the transistors M701 and M702 areconnected in common. A source S of the transistor M705 is connected tothe external terminal VC as a first power supply terminal and a drain Dthereof is connected to a drain D of the transistor M706. The commonconnection point between the drains D of the transistors M705 and M706is indicated by a node N73. A source S of the transistor M706 isconnected to the ground electric potential GND. The transistor M705 andthe transistor M706 form a CMOS inverter.

A gate G of the transistor M704 is connected to the node N73. Twothreshold values of the Schmitt trigger SH are set based on the ONresistance of each of the transistors M701, M702, M703, and M704. The ONresistance of each of the transistors M701, M702, M703, and M704 may bedetermined to set appropriate channel width and channel length of eachtransistor.

In addition, an input of the inverter INV74 is connected to the node N73and an output of the inverter INV74 is applied, as the output signal V7of the gate control circuit 7, to the gate G of the transistor M4.

Although the Schmitt trigger SH shown in FIG. 8 is employed for the gatecontrol circuit 7, this may be used for the gate voltage monitoringcircuit 5.

FIG. 9 is a circuit diagram showing a power module circuit device (IPM)100A applied to the present disclosure and conventional techniques. Thepower module circuit device 100A includes an upper driver 20. The upperdriver 20 includes the power semiconductor drive circuit 10 shown inFIGS. 1, 2, and 5 according to the present disclosure. The power modulecircuit device 100A further includes an RS flip-flop circuit 21, aunder-voltage protection circuit 22, resistors 23 and 24, NMOStransistors 25 and 26, a pulse generating circuit 27, a level shifter28, a boot current control circuit 29, a Schmitt trigger 30, a lowerdriver 31, a logic control circuit 32, a signal delay circuit 33, alevel shifter 34, a Schmitt trigger 35, an NMOS transistor 36, anabnormal signal generating circuit 37, a heat protection circuit 38, aunder-voltage protection circuit 39, a comparator 40 and a standardvoltage generating circuit 41. An external terminal KILL for applying akill signal Ki is not shown in the power module circuit device shown inFIG. 9.

The power module circuit device 100A shown in FIG. 9 further includes acapacitor CB and a diode DB. The capacitor CB and the diode DB form abootstrap circuit. A boot voltage VBB generated at a common connectionpoint between the capacitor CB and the diode DB is used as a powersupply voltage for driving the upper driver 20 and so on via theexternal terminal VB. The power module circuit device 100A is packagedin a DIP.

FIG. 10 shows results of comparison in driving loss between the powersemiconductor drive circuit 10 according to the present disclosure shownin FIG. 5 and the conventional power semiconductor drive circuit 10shown in FIG. 11 when these drive circuits are used for the power modulecircuit device 100A (IPM) shown in FIG. 9. The term “driving loss” usedherein refers to power obtained by subtracting output power from inputpower. For example, if the input power is 1[W] and the output power is0.9[W], the driving loss is 0.1[W] (=1−0.9). In FIG. 10, a horizontalaxis represents comparison between the conventional technique and thepresent disclosure when an effective value (rms) of the output currentid flowing in the transistor PT1 is 1[A], 2[A], and 4[A]. A verticalaxis represents normalized values of driving loss. Here, when theexisting driving loss is assumed as 1.00, the driving loss in thepresent disclosure is numerically expressed. A smaller driving lossvalue represents higher output power for the input power, i.e., higherpower efficiency. The driving loss is varied depending on a power supplyvoltage, an output current, a frequency of a driving signal, a controlscheme and so on. This comparison is made under the conditions where thevoltage VPP of the external terminal P as the second power supplyterminal is 400V, the voltage VCC of the external terminal VC as thefirst power supply terminal is 15V, the frequency of the driving signalis 5 kHz, and the control scheme is a PWM three-phase modulation scheme.

When the effective values of the output current id are 1[Arms], 2[Arms],and 4[Arms], the driving loss in the present disclosure is 0.70, 0.74,and 0.79, respectively. As the output current id increases, the ratio ofthe driving loss increases and the effect of reducing the driving lossis reduced slightly. However, it is found that the present disclosuresaves the power consumption by more than 20% than the conventionaltechnique.

According to the present disclosure in some embodiments, it is possibleto prevent gate driver deterioration and breakdown due to internalinductance according to a high-voltage, large-current and high-speedswitching, particularly at the time of transition from an ON state to anOFF state, prevent self-turning-on at the time of transition of an OFFstate to an ON state, and reduce switching loss.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the disclosures. Indeed, the novel methods and apparatusesdescribed herein may be embodied in a variety of other forms;furthermore, various omissions, substitutions and changes in the form ofthe embodiments described herein may be made without departing from thespirit of the disclosures. The accompanying claims and their equivalentsare intended to cover such forms or modifications as would fall withinthe scope and spirit of the disclosures.

INDUSTRIAL APPLICABILITY

As described above, the power semiconductor drive circuit, the powersemiconductor circuit, and the power module circuit device of thepresent disclosure can prevent gate driver breakdown due to aninductance component according to a high-voltage, large-current, andhigh-speed switching, particularly at the time of transition from an ONstate to an OFF state, prevent self-turning-on at the time ofturning-ON/OFF of a power semiconductor element, and suppress increasein switching loss. Thus, the present disclosure has very high industrialapplicability.

What is claimed is:
 1. A power semiconductor drive circuit comprising: aparallel circuit which is connected to a gate of a power semiconductorelement and is constituted by at least two transistors for setting gateresistance of the power semiconductor element; a gate voltage monitoringcircuit connected to the gate of the power semiconductor element and theparallel circuit, wherein a predetermined monitoring voltage is set inthe gate voltage monitoring circuit in order to monitor a gate voltageof the power semiconductor element; a signal delay circuit to delay anoutput signal of the gate voltage monitoring circuit; and a gate controlcircuit to change the magnitude of combined resistance of the parallelcircuit based on an output signal output from the signal delay circuit.2. The power semiconductor drive circuit of claim 1, wherein thecombined resistance of the parallel circuit is changed when the powersemiconductor element is turned off.
 3. The power semiconductor drivecircuit of claim 2, wherein the monitoring voltage is equal to or lessthan a mirror voltage of the power semiconductor element.
 4. The powersemiconductor drive circuit of claim 3, wherein the combined resistanceof the parallel circuit when the power semiconductor element is turnedoff is larger than the combined resistance of the parallel circuit whenthe power semiconductor element is in an OFF state.
 5. The powersemiconductor drive circuit of claim 4, wherein the combined resistanceof the parallel circuit is changed after a delay time set in the signaldelay circuit elapses.
 6. The power semiconductor drive circuit of claim1, wherein an ON state and OFF state of the gate voltage monitoringcircuit is controlled by a kill signal and an output signal of the gatevoltage monitoring circuit is a result of a logical AND operation forthe kill signal and the gate voltage applied to the power semiconductorelement.
 7. The power semiconductor drive circuit of claim 5, whereinthe gate voltage monitoring circuit is constituted by one or moreselected from a group consisting of a Schmitt trigger, a hysteresiscomparator, a window comparator, a comparator and an inverter.
 8. Thepower semiconductor drive circuit of claim 1, wherein the signal delaycircuit is an integration circuit including a resistor and a capacitor.9. The power semiconductor drive circuit of claim 5, wherein apredetermined threshold voltage is set in the gate control circuit andwherein the gate control circuit outputs a result of a logical ANDoperation for a driving signal applied to the gate of the powersemiconductor element and the output signal output from the signal delaycircuit.
 10. The power semiconductor drive circuit of claim 9, whereinassuming that a period from time t4, at which a mirror period of thegate voltage of the power semiconductor element is ended, to time t6, atwhich an output current flowing in the power semiconductor element issubstantially zeroed, is τ1 and a period from time t5, at which the gatevoltage becomes equal to the monitoring voltage, to time t8, at whichthe gate voltage becomes equal to the threshold voltage, is τ2, thecondition of τ2>τ1 is set.
 11. The power semiconductor drive circuit ofclaim 9, wherein the power semiconductor element includes an upper powertransistor connected to a power supply terminal and a lower powertransistor connected to a ground electric potential, the upper powertransistor being complementary to the lower power transistor, andwherein assuming that a period from time t5, at which a gate voltage ofthe upper power transistor becomes equal to the monitoring voltage, totime t8 at which the gate voltage of the upper power transistor becomesequal to the threshold voltage, is τ2 and time t 10 is a time at whichthe gate voltage of the upper power transistor when the lower powertransistor is in an ON state, becomes equal to the monitoring voltage,the relationship of (t10−t5)>τ2.
 12. The power semiconductor drivecircuit of claim 11, wherein assuming that a period from time t16, atwhich the gate voltage of the upper power transistor becomes equal tothe monitoring voltage, to time t20, at which the upper power transistorbegins to be turned off, is τ3 and a period from time t16, at which thegate voltage of the upper power transistor becomes equal to themonitoring voltage, to time t18, at which the threshold voltage set inthe gate control circuit becomes equal to the level of the output signalof the signal delay circuit, is τ4, the condition of τ3>τ4 is set. 13.The power semiconductor drive circuit of claim 9, wherein the gatecontrol circuit includes a first transistor, a second transistor, alogical AND circuit, a first node, a second node, and a third node,wherein a gate of the first transistor and a first end of the logicalAND circuit are connected to the first node, wherein a drain of thefirst transistor, a drain of the second transistor, and a second end ofthe logical AND circuit are connected to the second node, wherein anoutput terminal of the logical AND circuit and a gate of the secondtransistor are connected to the third node, and wherein the drivingsignal is applied to the first node and an output signal of the signaldelay circuit is output to the second node.
 14. A power semiconductorcircuit comprising: a power semiconductor drive circuit of claim 1; anda power semiconductor element having a gate driven by the powersemiconductor drive circuit.
 15. The power semiconductor circuit ofclaim 14, wherein the power semiconductor element is a MOS transistor orIGBT.
 16. The power semiconductor circuit of claim 15, wherein the powersemiconductor element is made of one selected from a group consisting ofsilicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
 17. Thepower semiconductor circuit of claim 16, wherein the power semiconductorelement further includes a diode, and wherein the diode is made of oneselected from a group consisting of silicon (Si), silicon carbide (SiC),and gallium nitride (GaN).
 18. The power semiconductor circuit of claim15, wherein the lower power transistor is made of one selected from agroup consisting of silicon (Si), silicon carbide (SiC), and galliumnitride (GaN).
 19. The power semiconductor circuit of claim 15, whereinthe upper power transistor and the lower power transistor are fabricatedon separate semiconductor substrates, and wherein a drain-sourceconduction path of the upper power transistor and a drain-sourceconduction path of the lower power transistor are coupled in seriesbetween the power supply terminal and the ground electric potential. 20.The power semiconductor circuit of claim 15, wherein the powersemiconductor circuit is used for one selected from a group consistingof inverters for converting DC into AC, one or more motor drivecircuits, and switching power supply devices.
 21. A power module circuitdevice comprising: the power semiconductor circuit of claim 14; and atleast one electronic element constituting at least a bootstrap circuit.22. The power module circuit device of claim 21, wherein the powermodule circuit device is packaged in a single dual-line package.